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ME54BS62 — nRF54L15 MCU module (evaluated candidate)

MinewSemi ME54BS62-1Y15TE — pin-complete candidate from the Rev B2 ECN-19 investigation. Not selected: the measured pattern has deep nulls and the small on-module antenna-GND area makes performance host-layout-sensitive (Minew's own assessment concurs). Documented for reference: the only Minew module with integrated antenna exposing all 30 GPIOs incl. P1.15.

Antenna measurements (Minew eval board)

From ME54BS62 ANT V1.0a: peak gain −0.70 dBi / efficiency 42 % (@~2455), ~39 % @ 2480 (centered, flat) → TRP ≈ +4.2 dBm mid-band / +3.9 dBm @ 2480 at +8 dBm TX. Pattern: deep nulls (−20 dB+) along one axis (E-planes) → orientation-dependent dropouts for tags; tiny on-module GND makes eval-board numbers best-case on real hosts.

Minew's alternative for ultra-small: ME54BS61

For small size without RF sacrifice Minew recommends ME54BS61 (6.0 × 6.0 × 1.8 mm, CSP, no integrated antenna — RF pin for on-board or external antenna, max +8 dBm). It fails EverTag's integrated-antenna requirement for the second-source track, but is the preferred candidate for the own-antenna / long-term track (232240–259 blocks): its Single Modular FCC grant + BQB mean the antenna is designed on our PCB under Minew's grant (use the filing's antenna type at equal/lesser gain, per reference layout) instead of certifying a bare-chip radio from scratch. Request Minew's reference antenna design + FCC-filing antenna list before committing. Its certs are in repo: FCC 2BDJ6-ME54BS61 (grant, Single Modular, 2026-06-07), CE verification, BQB DN Q394122 (shared with ME54BS62). Its datasheet rev 1.1.0 contains an antenna example (§7: ME54BE61 adapter, ~18 × 8 mm edge trace antenna, 50 Ω feed — explicitly disclaimed as end-product reference) and PCB rules (§8) that require the RF side to face the board edge ("central area strictly prohibited"), 4 mm RF keep-out, 20 mm to DC-DC converters, and ≥50 mm to other radio modules (ESP32-C5 on gateway variants!). FCC-filing antenna resolved (2026-08-18): the grant was obtained with a third-party external 3 dBi monopole (Xiangboyi XBY200674-C/D, 2400–2500 MHz, VSWR ≤ 1.5, via IPEX on the BE61 adapter — exhibit, fccid.io). Per FCC modular rules (§15.212/KDB 996369) this sets the antenna envelope: same type (monopole family) at ≤ 3 dBi is covered — which a PCB IFA (0–2 dBi typ.) satisfies. To make it bulletproof: document the same-type/lesser-gain rationale in the technical file, use Minew's offered FAE layout review, and preferably ask Minew to C2PC-add our PCB antenna to their grant. Minew also clarified (2026-08-18) that edge placement is a performance recommendation, not a hard rule.
Manufacturer Shenzhen Minewsemi Co., Ltd.
Ordering code ME54BS62-1Y15TE (PCB antenna, onboard 32.768 kHz crystal, nRF54L15, external-RF pad option)
SoC Nordic nRF54L15 WLCSP (explicit in datasheet) — 1.5 MB NVM / 256 KB RAM
Dimensions 6.0 × 9.0 × 1.8 mm (−47 % area vs PAN B611-1)
Package style Bottom pad grid A1–G7 (LGA-style, gaps at C3–C5/D3–D5/E3–E5) — no optical inspection of joints; X-ray plan required
Antenna Integrated PCB antenna; pad A1 (RF) for external option — leave N/C
Crystals 32 MHz + 32.768 kHz onboard (Y code)
TX / RX −40…+8 dBm (CSP package supports +8 per Nordic; QFN-based modules are capped at +7) / −96 dBm @ 1 Mbps · range 10–70 m — but weak radiated performance per Minew (antenna GND area)
Supply 1.7–3.6 V (≥ 2.3 V recommended for RF)
Currents TX 5 mA @ 0 dBm, RX 3.2 mA; sleep currents not published
Temp range −40…+105 °C
GPIO exposed 30 — complete for the EverTag superset incl. P1.15
Certifications FCC 2BDJ6-ME54BS62 (grant, Single Modular, Part 15C, 2026-07-10, 0.006 W conducted) · CE verification · BQB DN Q394122 (cert, 2026-08-10, shared with ME54BS61) · no ISED/SRRC/TELEC received
Sourcing MinewSemi store only (no distributor stock found); ME54BE62 devkit available
Datasheet ME54BS62 Datasheet (local) · Product page

Module pad ↔ nRF54 GPIO mapping

Verify pad order against the datasheet drawing

The datasheet lists several pads per grid row (e.g. "F1–F7: P0.03/P2.09/P2.08/P1.09/P1.11/P1.14/P1.05"). The per-pad assignment below follows list order — confirm each pad against the mechanical drawing before schematic entry, especially rows A and G.

Pad Signal Pad Signal
A1 RF (N/C — internal antenna used) E1 P0.02
A2 GND E2 P2.10
A3 P2.04 E6 P1.04 (AIN0)
A4 P2.05 E7 GND
A5 P2.03 F1 P0.03
A6 P2.01 F2 P2.09
A7 P2.00 F3 P2.08
B1 GND F4 P1.09
B2 P2.06 F5 P1.11 (AIN4)
B3 SWDIO F6 P1.14 (AIN7)
B4 SWCLK F7 P1.05 (AIN1)
B5 P2.02 G1 P0.04
B6 P1.07 (AIN3) G2 P2.07
B7 P1.08 G3 GND
C1 P0.00 G4 P1.10
C2 RST G5 P1.12 (AIN5)
C6 P1.03 / NFC2 G6 P1.13 (AIN6)
C7 P1.06 (AIN2) G7 P1.15
D1 P0.01 — —
D2 GND — —
D6 P1.02 / NFC1 — —
D7 VCC — —

Grid positions C3–C5, D3–D5, E3–E5 have no pads listed. P1.00/P1.01 (LFXO) are internal to the module.

Layout & process notes (from datasheet)

  • ≥ 4 mm clearance around the antenna end; module at PCB edge recommended; no copper under the antenna area; ferrite-bead isolation suggested on supply.
  • Stencil 0.10–0.12 mm, pin-1 aperture 0.9:1 not expanded; single reflow pass recommended on the module side; max 260 °C; MSL bake rules per datasheet if exposed >168 h @ 85 °C/60 %RH or stored >1 year.
  • WLCSP-based module — confirm production programming (SWD via B3/B4) and any chip-variant implications with Minew before committing.