MCU Modules — nRF54L15¶
The nRF54 platform (Tag 230220+, Station 232200+) uses an nRF54L15 MCU module as U1. Board documentation references signals by nRF54 GPIO name only — each module page owns the GPIO ↔ physical-pin mapping, so a module change never touches the board pin tables.
| Module | Role | Articles | Page |
|---|---|---|---|
| Panasonic PAN B611-1 (ENW89861B01F) | Active — Rev B1 | 230220, 232200–232204 | pan-b611 |
| Raytac AN54LV-15 | Selected second source — B2 (2026-08-20; gate: Raytac volume pricing) | 232220–232224, 230240 (reserved) | an54lv-15 |
| MinewSemi ME54BS62 (ME54BS62-1Y15TE) | Evaluated — not selected (pin-complete but weak RF per Minew; ME54BS61-4Y15TE noted for the own-antenna track) | — | me54bs62 |
| Raytac AN54LV-P15 (PCB ant.) / AN54LV-K15 (ANT pad — own-antenna track) | Sibling variants, same certs incl. ISED | — | datasheets |
Function-per-board for every GPIO: GPIO Mux Master Table. Second-sourcing rationale and decisions: Rev B2 ECN-19. Article blocks: Article Numbering.
Cross-module pin reference¶
Rev B1 function per GPIO (Tag / Station / Gateway variants), with the physical pin on each module. ⚠️ ME54BS62 pad letters follow datasheet list order — verify against the drawing before schematic entry (see me54bs62).
| nRF54 GPIO | B1 function | PAN B611-1 | AN54LV-15 | ME54BS62 |
|---|---|---|---|---|
| P0.00 | B_VARIANT | A3 | 5 | C1 |
| P0.01 | LED_DATA (Tag: red LED) | 1 | 4 | D1 |
| P0.02 | UART0 TX | 2 | 7 | E1 |
| P0.03 | UART0 RX | 3 | 3 | F1 |
| P0.04 | Service button / SW1 | 4 | 2 | G1 |
| P1.00 | LFXO — crystal inside PAN/Minew modules; external on host PCB for AN54LV | D1 | 33 (XL1) | — |
| P1.01 | LFXO — crystal inside PAN/Minew modules; external on host PCB for AN54LV | E1 | 32 (XL2) | — |
| P1.02 | ACC SCK / UART1 TX (GW) / sensor SCK | 15 | 29 | D6 |
| P1.03 | ACC MISO / UART1 RX (GW) / sensor MISO | 14 | 27 | C6 |
| P1.04 | I2C SCL (AIN0) | 13 | 25 | E6 |
| P1.05 | I2C SDA (AIN1) | 12 | 23 | F7 |
| P1.06 | BAT_VOLTAGE (AIN2) | 11 | 22 | C7 |
| P1.07 | V_SAMPLE (AIN3) | 10 | 21 | B6 |
| P1.08 | ACC CS / sensor CS | B4 | 19 | B7 |
| P1.09 | ST25DV.GPO | A1 | 38 | F4 |
| P1.10 | ACC MOSI / ESP32_RESET (GW) / sensor MOSI | A2 | 41 | G4 |
| P1.11 | ACC INT1 / ESP32_READY (GW) / sensor INT (AIN4) | B3 | 39 | F5 |
| P1.12 | EXT_DETECT (AIN5) | B1 | 37 | G5 |
| P1.13 | ACC INT2 / DC_PRESENT (AIN6) | B2 | 35 | G6 |
| P1.14 | CHARGE_STATUS / available (AIN7) | C2 | 36 | F6 |
| P1.15 | ST25DV.LPD (PAN611 boards) | C1 | 34 | G7 |
| P2.00 | COEX_REQUEST (GW, polled) | C4 | 12 | A7 |
| P2.01 | COEX_PRIORITY (GW, polled) | E4 | 17 | A6 |
| P2.02 | COEX_GRANT (GW) | D4 | 24 | B5 |
| P2.03 | available (freed in B1) | E3 | 26 | A5 |
| P2.04 | available (freed in B1) | D3 | 14 | A3 |
| P2.05 | available / ST25DV.LPD on Minew articles | C3 | 10 | A4 |
| P2.06 | available (freed in B1) | 18 | 16 | B2 |
| P2.07 | available (freed in B1) | 19 | 18 | G2 |
| P2.08 | available (freed in B1) | 20 | 8 | F3 |
| P2.09 | available (freed in B1) | 21 | 13 | F2 |
| P2.10 | ST25DV.VCC | 22 | 6 | E2 |
| SWDIO | Debug (J1/P1 TC2030) | 6 | 9 | B3 |
| SWDCLK | Debug (J1/P1 TC2030) | 5 | 11 | B4 |
| nRESET | Reset (100k PU, TP8) | 23 | 43 | C2 |
| VCC | Supply | 16 | 20 (VDD_NRF) | D7 |
| GND | Ground | 8, 9, 17, A4, D2, E2 | 1, 15, 31, 40, 42, 44–55 | A2, B1, D2, E7, G3 |
| RF | External-antenna option — N/C (internal antenna used) | 7 | — (no RF pin) | A1 |
Same pin number ≠ same signal across modules
Pin designators collide between modules with different meanings (e.g. C1 = P1.15 on PAN B611-1 but P0.00 on ME54BS62). Always key schematics and reviews on the GPIO name, never on the module pin designator.
Shared facts (all three)¶
- PAN B611-1 and ME54BS62 have integrated antenna (RF pin left N/C) and onboard 32.768 kHz crystal (tolerance/ppm not published by any vendor — open supplier question). Raytac AN54LV-xx has no onboard LF crystal: host PCB adds a crystal on XL1/XL2 (nRF54L15 has internal configurable load caps, so external caps may be omitted). Today no EverTag PCB carries an LFXO footprint.
- Wirepas Mesh crystal requirement (verified from Wirepas "Crystal Requirements" table, 2026-08-19): LFXTAL 32.768 kHz ± 20 ppm @ +25 °C, −0.04 ppm/°C² temperature bias, ±3 ppm/year aging. Clock error widens the TDMA RX guard windows → higher idle current, so the modules' unpublished internal-crystal ppm is a battery-budget question for the vendors. nRF54L15 LFXO additionally requires CL 6–9 pF, C0 ≤ 2.0 pF, ESR ≤ 100 kΩ (DS v1.0) — NB: common 12.5 pF crystals are not usable.
- Same SoC: both firmware builds run unchanged; module identity is programmed to UICR by the production jig (TX-power cap + labeling) — ECN-19 §8.
- TX power is package-inherent (nRF54L15 DS v1.0: CSP47 = 8 dBm + P1.15, QFN48 = 7 dBm without P1.15). All modules in the table are CSP47-based → +8 dBm across the platform, one firmware TX table. UICR module-ID retained for traceability/labeling.